1. Field of Invention
The invention relates to a decoder and its associated decoding method, and in particular to a variable length decoder and method of implementing the same, that is utilized to restore the correct output result through integrating a plurality of decoding look-up-table tables into a single reordered index decoding look-up-table in cooperation with compensation value calculation through mapping of the reordered index value.
2. Related Art
In the processing of the dynamic image compression, the process of decoding the codeword string usually requires utilization of the Variable Length Decoding (VLD) technology.
In the hardware design of ordinary variable length decoder, it usually includes the VLD designed according to the requirement of a plurality of different decoding look-up tables. In the actual implementation of VLD, after decoding and obtaining the corresponding index value by the respective VLD index decoder, the corresponding output result is obtained from the corresponding LUT by making use of the respective index value. Finally, the output results required are obtained through a multiplexer based on the previous decoding results.
As shown in FIG. 1, upon entering into a variable length decoder by a codeword string 50, then depending on the number of LUT's required for decoding, the corresponding number VLD index decoders 110, 111 are utilized to generate the respective index values (a first index value 113 and a second index value 115), these index values are then sent into the corresponding LUT 120, 121 to proceed with the search for the output results (a first output result 123 and a second output result 125). And finally, a multiplexer 130 is utilized to search and find out the output result 55 actually required from among the various different output results based on the previous decoding information. Since, in general, in the hardware realization of Variable Length Decoder, the creation of LUT is realized through a Read Only Memory (ROM), a Content Address Memory (CAM), or a Programmable Logic Array (PLA). Supposing that the maximum-bit-length used for decoding is n, and in case that LUT is realized by making use of ROM, then a table of 2n items is required, thus resulting in a huge waste of large amount memory space. Even if the LUT is realized through CAM or PLA, the number of table items required is equivalent to the number of data items to be decoded.
In the past, the improvement proposed concerning the Variable Length Decoder and its decoding method is aimed at determining how to simplify the data items contained in a single LUT. By doing so, the benefit of reducing the memory space and logic gates used can be achieved, in case that a single LUT is utilized in decoding. However, in case that two (or more) LUT's are utilized for decoding and that the ratio is high for the same output result, the effect of reducing the memory space and logic gates required by this approach is rather limited and requires further improvements.